DocumentCode
3156851
Title
Charge loss associated with program disturb stresses in EPROMs
Author
Miller, T. ; Illyes, S. ; Baglee, D.A.
Author_Institution
Intel Corp., Rio Rancho, NM, USA
fYear
1990
fDate
27-29 March 1990
Firstpage
154
Lastpage
158
Abstract
Program disturb or V/sub t/ shifts due to bit line stress for EPROMs continues to be a major reliability issue among semiconductor manufacturers, but very little information exists on these mechanisms. It is shown that program disturb is a defect mechanism, and the effects of voltage and temperature are studied. The impact on programming and extended read cycles is also evaluated.<>
Keywords
EPROM; circuit reliability; failure analysis; integrated circuit technology; life testing; EPROMs; LOCOS processing; V/sub t/ shifts; bit line stress; defect mechanism; extended read cycles; major reliability issue; program disturb stresses; programming; semiconductor manufacturers; EPROM; Electrons; Life estimation; Nonvolatile memory; Production; Semiconductor device manufacture; Semiconductor device reliability; Stress; Temperature; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 1990. 28th Annual Proceedings., International
Conference_Location
New Orleans, LA, USA
Type
conf
DOI
10.1109/RELPHY.1990.66079
Filename
66079
Link To Document