Application of smart pixels to digital image halftoning

Author

Sayles, Andre H. ; Shoop, Barry L.

Author_Institution

Photonics Res. Center, United States Mil. Acad., West Point, NY, USA

Volume

1

fYear

1996

fDate

3-6 Nov. 1996

Firstpage

492

Abstract

An innovative circuit for digital image halftoning applications has been implemented in several different hybrid fabrication processes. The circuits have been demonstrated to be compatible with several approaches to smart pixels and offer a wide range of options for realizing optical inputs and outputs. The 0.8 micron n-well CMOS process at MOSIS has been used in conjunction with SEED technology to implement a digital image halftoning algorithm that offers the potential for higher quality binary images. Similar algorithms have also been implemented using combined CMOS and liquid crystal on silicon processes as well as the Vitesse H-GaAs III foundry process.

Keywords

CMOS digital integrated circuits; MESFET integrated circuits; SEEDs; VLSI; application specific integrated circuits; digital signal processing chips; image processing; integrated optoelectronics; liquid crystal devices; neural chips; smart pixels; 0.8 micron; GaAs; MOSIS; SEED technology; Si; Vitesse H-GaAs III foundry process; binary images; combined CMOS and liquid crystal on Si processes; digital image halftoning; error diffusion modulator; hybrid fabrication processes; n-well CMOS process; optical inputs; optical outputs; smart pixels; Circuits; Digital images; Integrated optics; Liquid crystal on silicon; Optical feedback; Optical filters; Optical network units; Optical signal processing; Signal processing algorithms; Smart pixels;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1996. Conference Record of the Thirtieth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-8186-7646-9

Type

conf

DOI

10.1109/ACSSC.1996.600969

Filename

600969