DocumentCode :
3156892
Title :
Via Minimization for Gridless Layouts
Author :
Naclerio, N.J. ; Masuda, S. ; Nakajima, K.
Author_Institution :
Electrical Engineering Department and Systems Research Center, University of Maryland, College Park, MD
fYear :
1987
fDate :
28-1 June 1987
Firstpage :
159
Lastpage :
165
Abstract :
This paper describes a graph theoretic algorithm which, given a particular layout, finds a layer assignment that requires the minimum number of vias. The time complexity of the algorithm is O(n 3) where n is the number of routing segments in the given layout. Unlike previous algorithms, this algorithm does not require the layout to be grid based and places no constraints on the location of vias or the number of wires that may be joined at a single junction. The algorithm yields globally optimum results when the maximum junction degree is limited to three and has been fully implemented.
Keywords :
Degradation; Educational institutions; Integrated circuit interconnections; Manufacturing; Minimization; Nonhomogeneous media; Permission; Printed circuits; Routing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1987. 24th Conference on
ISSN :
0738-100X
Print_ISBN :
0-8186-0781-5
Type :
conf
DOI :
10.1109/DAC.1987.203237
Filename :
1586221
Link To Document :
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