FPGA implementations of the ICEBERG block cipher

Author

Standaert, François-Xavier ; Piret, Louvain-La-NeuvGilles ; Rouvroy, Gael ; Quisquater, Jean-Jacques

Author_Institution

UCL, Louvain-La-Neuve, Belgium

Volume

1

fYear

2005

fDate

4-6 April 2005

Firstpage

556

Abstract

This paper presents FPGA (field programmable gate array) implementations of ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efficient combinations of encryption/decryption. The implementations proposed also allow changing the key and encrypt/decrypt (E/D) mode for every plaintext, without any performance loss. In comparison with other recent block ciphers, the implementation results of ICEBERG show a significant improvement of hardware efficiency. Moreover, the key and E/D agility allows considering new encryption modes to counteract certain side-channel attacks.

Keywords

cryptography; field programmable gate arrays; reconfigurable architectures; FPGA; ICEBERG block cipher; decryption; encryption; field programmable gate array; key changing; plaintext; reconfigurable hardware; side-channel attacks; Cryptography; Electronic mail; Feedback loop; Field programmable gate arrays; Hardware; NIST; Performance loss; Software performance; Table lookup; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Technology: Coding and Computing, 2005. ITCC 2005. International Conference on

Print_ISBN

0-7695-2315-3

Type

conf

DOI

10.1109/ITCC.2005.155

Filename

1428521