A divided decoder-matrix (DDM) structure and its application to a 8 kb GaAs MESFET ROM

Author

Kanan, Riad ; Guyot, Alairc ; Hochet, Bertrand ; Declercq, Michel

Author_Institution

Electron. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland

Volume

3

fYear

1997

fDate

9-12 Jun 1997

Firstpage

1888

Abstract

This paper describes a new approach which allows the realization of both low-power and high storage capacity ROMs in GaAs. In this technique, called DDM (Divided Decoder Matrix), low-power operation is obtained by powering down the parts which are not situated in the addressing path, while high-storage capability is obtained by limiting the leakage currents in the ROM matrix. As an application of the DDM technique, an 8 Kbit MESFET ROM has been designed with a standard 0.6 μm-gate MESFET process. The ROM has a typical access time of 1.2 ns and a power dissipation of 60 mW

Keywords

III-V semiconductors; MESFET integrated circuits; decoding; field effect memory circuits; gallium arsenide; leakage currents; random-access storage; 0.6 micron; 1.2 ns; 60 mW; 8 Kbit; GaAs; GaAs MESFET ROM; ROM matrix; divided decoder-matrix structure; high storage capacity ROMs; leakage current limitation; low-power ROMs; low-power operation; Decoding; Distributed decision making; Gallium arsenide; Leakage current; Logic; MESFETs; MOSFETs; Power dissipation; Read only memory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.621518

Filename

621518