A new high-resolution, temperature-compensated cyclic time-to-digital converter

In this paper, we propose a new high-resolution, temperature-compensated cyclic CMOS time-to-digital converter. To achieve the requirements for high resolution and wide range, we presented a modified architecture such that the fine measurement is obtained by a residual encoder which measures the incomplete delay cycle at the end of the input pulse. By this way, the resulting resolution is almost equivalent to the delay of the delay cell. This system was designed and fabricated in TSMC CMOS 0.35 um 2P4M process with the core area of 680times760 um². The range of the measurement, in the temperature between 0degC and 100degC, can be up to 10 mus with a resolution of 80 ps and a power consumption of 1.88 mW.