Title :
Design of a low power Delay Locked Loop based Clock and Data Recovery circuit
Author :
Kumar, Vivek ; Khosla, Mamta
Author_Institution :
Dept. of Electron. & Commun. Eng., Dr. B. R. Ambedkar Nat. Inst. of Technol., Jalandhar, India
Abstract :
A low power Delay Locked Loop based Clock and Data Recovery circuit has been designed in this paper. A standby filter is a novel feature in this design. Level tracking technique is used for data recovery. The circuit is designed using Verilog HDL. The layout of the circuit is generated and verified using Cadence SoC Encounter. Total die area and total dynamic power dissipation of the circuit is 0.01mm2 and 799.8643μW respectively at 1.8V power supply.
Keywords :
circuit layout; clock and data recovery circuits; delay lock loops; low-power electronics; Cadence SoC Encounter; Verilog HDL; circuit layout; clock-and-data recovery circuit; level tracking technique; low-power delay locked loop design; power 799.8643 muW; standby filter; voltage 1.8 V; Clocks; Computer architecture; Delay; Hardware design languages; Multiplexing; Phase locked loops; Power dissipation; Delay Locked Loop; Level Tracking; Standby Filter; one-hot multiplexer;
Conference_Titel :
India Conference (INDICON), 2011 Annual IEEE
Conference_Location :
Hyderabad
Print_ISBN :
978-1-4577-1110-7
DOI :
10.1109/INDCON.2011.6139507
