Title :
A logic gate for reversible pipelining
Author :
Jung, Keewook ; Kim, Wonchan
Author_Institution :
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
Abstract :
This paper describes a logic gate for reversible pipelining that needs about 2×(number of input signals) of transistors and 4-phase clock, which is approximately half of those of other circuits either in transistor count or in clock phase. Simulation results of a 2-stage shift register based on this gate show that this implementation with a clock generator dissipates 59% less power than the theoretical power dissipation lower limit of conventional CMOS implementations
Keywords :
CMOS logic circuits; logic design; logic gates; pipeline processing; shift registers; 2-stage shift register; 4-phase clock; CMOS implementation; clock generator; logic gate; reversible pipelining; CMOS logic circuits; Circuit simulation; Clocks; Logic circuits; Logic gates; MOSFETs; Pipeline processing; Shift registers; Switches; Voltage;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.621528
