Title :
Low power multiplication schemes for single multiplier CMOS based FIR digital filter implementations
Author :
Erdogan, A.T. ; Arslan, T. ; Horrocks, D.H.
Author_Institution :
Sch. of Eng., Univ. of Wales, Cardiff, UK
Abstract :
Two multiplication schemes are investigated for the low power implementation of FIR filters through the reduction of switching activity within the multiplier section of the filters. The schemes, which target single multiplier CMOS based DSP processors, are used with transpose direct form filter structure and their switching activities are compared
Keywords :
CMOS digital integrated circuits; FIR filters; VLSI; digital arithmetic; digital filters; digital signal processing chips; multiplying circuits; CMOS based DSP processors; CMOS based digital filter implementations; FIR digital filter; low power multiplication schemes; single multiplier digital filter implementation; switching activity reduction; transpose direct form filter structure; CMOS logic circuits; Clocks; Clouds; Delay; Digital filters; Digital signal processing; Digital signal processing chips; Finite impulse response filter; Power dissipation; Power engineering and energy;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.621531
