A parallelized design for an elliptic curve cryptosystem coprocessor

In many applications a software implementation of ECC (elliptic curve cryptography) might be inappropriate due to performance requirements, therefore hardware implementations are needed. We present some results about a novel hardware implementation for ECC, that introduces also a form of parallelism to maximize the use of function units and hence to improve the throughput. Then we propose a comprehensive comparison of this new architecture with both some RSA architectures and other ECC implementations in ASIC VLSI technology.