Repeater design to reduce delay and power in resistive interconnect

In large chips, the propagation delay of the data and clock signals is limited due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing short-circuit current. Design equations for determining the optimum number of repeaters to be inserted along a resistive interconnect line for reduced delay are presented. Power dissipation in repeater chains is also analyzed. The analytical model used in these design equations is based on the α-power law I-V equations for modeling short-channel devices and exhibits a maximum error of 16% for typical RC loads as compared to SPICE