DocumentCode :
315774
Title :
Efficient memory management techniques to speed up the conventional transient simulation of piecewise linear circuits including power electronics
Author :
Leelarasmee, Ekachai ; Hwangkhunnatham, Methee
Author_Institution :
Dept. of Electr. Eng., Chulalongkorn Univ., Bangkok, Thailand
Volume :
2
fYear :
1997
fDate :
9-12 Jun 1997
Firstpage :
941
Abstract :
The transient simulation of piecewise linear circuits, including power electronics, using traditional simulation algorithms is revised by adding a dynamic memory management technique called LU matrix cache. It makes use of free main memory to store past copies of LU factors for future reuse. This technique can be easily added to a general purpose circuit simulator to increase its execution speed significantly when applied to piecewise linear circuits. Furthermore, a matrix partition technique is presented to reduce the storage requirement of multiple LU factors by storing only parts that change from one iteration to another
Keywords :
circuit analysis computing; iterative methods; nonlinear network analysis; piecewise-linear techniques; power electronics; storage management; transient analysis; LU matrix cache; circuit simulator; execution speed; iteration; matrix partition technique; memory management techniques; piecewise linear circuits; power electronics; storage requirement; transient simulation; Capacitors; Circuit simulation; Computational modeling; Diodes; Equations; Memory management; Piecewise linear approximation; Piecewise linear techniques; Power electronics; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
Type :
conf
DOI :
10.1109/ISCAS.1997.621869
Filename :
621869
Link To Document :
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