100-Gb/s three-parallel Reed-Solomon based foward error correction architecture for optical communications

Author

Lee, Hanho ; Choi, Chang-Seok ; Shin, Jongyoon ; Ko, Je-Soo

Author_Institution

Dept. of Inf. & Commun. Eng., Inha Univ., Incheon

Volume

01

fYear

2008

fDate

24-25 Nov. 2008

Abstract

This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-mum CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300 MHz and has a throughput of 115-Gb/s for 0.13-mum CMOS technology.

Keywords

CMOS integrated circuits; Reed-Solomon codes; decoding; forward error correction; high-speed optical techniques; optical fibre communication; CMOS standard cell technology; RS(255,239) decoder; Reed-Solomon decoder; bit rate 100 Gbit/s; bit rate 115 Gbit/s; foward error correction; frequency 300 MHz; high-speed decoder; optical communications; size 0.13 mum; three-parallel architecture; voltage 1.2 V; CMOS technology; Clocks; Decoding; Error correction; Forward error correction; Frequency; Optical fiber communication; Reed-Solomon codes; Throughput; Voltage; CMOS; Reed-Solomon code; archtecture; forward error correction; optical communications;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference, 2008. ISOCC '08. International

Conference_Location

Busan

Print_ISBN

978-1-4244-2598-3

Electronic_ISBN

978-1-4244-2599-0

Type

conf

DOI

10.1109/SOCDC.2008.4815623

Filename

4815623