FPGA based asynchronous pipelined viterbi decoder using two phase bundled-data protocol

In this paper a novel approach is proposed for the implementation of asynchronous pipelined circuits. In this approach, Synchronous FPGAs form Xilinx and Altera are used for implementing the asynchronous pipelined Circuits using two phase bundled data protocol. Asynchronous pipelined circuits have many potential advantages over their synchronous equivalents including lower latency, lower power consumption, high throughput, avoiding clock skew problem, etc., In this proposed approach, Muller C-element is used to generate the control signals in the handshaking circuit and Double Edge Triggered D-flip-flop (DETDFF) is used to ensure the two phase operation of the control signal generation. To verify the efficacy of this approach, an asynchronous pipelined 4 state, frac12-rate viterbi decoder is implemented on Cyclone II FPGA using Quartus II Altera tool. The throughput of asynchronous pipelined Viterbi decoder using the proposed approach is 181Mbps which is 2.83 times greater than that of the synchronously pipelined Viterbi decoder with 35% increase in area.