Automatic generation of diagrams for system-on-chip architectures

The automatic generation of diagrams for gate networks has been practically used in the HDL based design for decades. Unfortunately, these diagrams are losing their popularity since they have failed to satisfy the requirements that have been newly brought up in the system level. The related issues include (i) the irregularity of blocks, (ii) the large number of block pins, and (iii) the complicated interconnection which is domineered by the bus architectures. These buses are globally distributed and shared by most blocks. The conventional topological ordering which assumes the left-to-right signal flows is simply not working, any more. We propose a fish-bone style topological construct which is popular to hand-drawn diagrams, but imposes a new combinatorial problem on the CAD research and development. A heuristic algorithm has been developed and implemented to solve this problem and validated on industrial- strength system-level designs.