Automatic 3D wire loop tracing in computed tomography images using extended generalized cylinder modeling

Automobile industry requires 100% inspection of every electronic component used. If a wire bonding device has a failure rate of 1 ppm, it would have the consequence of 15 of 1000 cars would fail. In this paper, we propose a method for tracing and inspecting 3D wire loops in a sealed semiconductor device using X-ray CT. 3D primitives are detected in predefined planes with a subpixel transition detection algorithm. Potential wire centroids are then calculated with deformable generalized cylinders employing an adaptive shape constraint to minimize the interferences from beam-hardening artifacts. Tracing of wires are performed in 2D projection space and mappings are done to find 3D correspondences. To test the capability of the software, we scanned semiconductor wirebond devices with a low resolution X-ray CT system and process slices at present of large amount of artifacts. It is shown that wire loops can be detected reliably with sub-voxel accuracy. The processing time for 10 wires is 30 seconds (using a laptop with Intel dual core 1,6 G processor).