Title :
Soft error resilient VLSI architecture for signal processing
Author :
Alnajjar, Dawood ; Ko, Younghun ; Imagawa, Takashi ; Hiromoto, Masayuki ; Mitsuyama, Yukio ; Hashimoto, Masanori ; Ochi, Hiroyuki ; Onoye, Takao
Author_Institution :
Dept. Inf. Syst. Eng., Osaka Univ., Suita, Japan
Abstract :
This paper presents a reliability-configurable coarse-grained reconfigurable array for signal processing, which offers flexible reliability to soft error. A notion of cluster is introduced as a basic element of the proposed reconfigurable array, each of which can select one of four operation modes with different levels of spatial redundancy and area-efficiency. Evaluation of permanent error rates demonstrates that four different reliability levels can be achieved by a cluster of the reconfigurable array. A fault-tolerance evaluation of Viterbi decoder mapped on the proposed reconfigurable array demonstrates that there is a considerable trade-off between reliability and area overhead.
Keywords :
VLSI; Viterbi decoding; array signal processing; error analysis; fault tolerance; integrated circuit reliability; reconfigurable architectures; VLSI architecture; Viterbi decoder; area-efficiency; fault-tolerance evaluation; permanent error rates; reliability-configurable coarse-grained reconfigurable array; signal processing; soft error resilient; spatial redundancy; Application software; Array signal processing; Circuits; Error correction; Error correction codes; Power system reliability; Reconfigurable architectures; Redundancy; Signal processing; Very large scale integration;
Conference_Titel :
Intelligent Signal Processing and Communication Systems, 2009. ISPACS 2009. International Symposium on
Conference_Location :
Kanazawa
Print_ISBN :
978-1-4244-5015-2
Electronic_ISBN :
978-1-4244-5016-9
DOI :
10.1109/ISPACS.2009.5383872