DocumentCode
3158329
Title
A new approach for circuit design optimization using Genetic Algorithm
Author
Bao, Zhiguo ; Watanabe, Takahiro
Author_Institution
Grad. Sch. of Inf. Production & Syst., Waseda Univ., Kitakyushu
Volume
01
fYear
2008
fDate
24-25 Nov. 2008
Abstract
A circuit designed by human often results in very complex hardware architectures, requiring a large amount of manpower and computational resources. A wider objective is used to find novel solutions to design such complex architectures so that system functionality and performance may not be compromised. Design automation using reconfigurable hardware and evolutionary algorithms (EA), such as genetic algorithm (GA), is one of the methods to tackle this issue. This concept applies the notion of Evolvable Hardware (EHW) to the problem domain such as novel design solutions and circuit optimization. EHW is a new field about the use of EA to synthesize a circuit. EA manipulates a population of individuals where each individual describes how to construct a candidate for a good circuit. Each circuit is assigned a fitness, which indicates how well a candidate satisfies the design specification. EA uses stochastic operators repeatedly to evolve new circuit configurations from existing ones, and a resultant circuit configuration will exhibit a desirable behavior. In this paper, optimum circuit design by using GA with fitness function composed of circuit complexity, power and time delay is proposed, and its effectiveness is shown by simulations.
Keywords
genetic algorithms; integrated circuit design; optimisation; circuit configurations; circuit optimization; complex hardware architectures; evolutionary algorithms; evolvable hardware; genetic algorithm; reconfigurable hardware; Circuit optimization; Circuit synthesis; Computer architecture; Design automation; Design optimization; Evolutionary computation; Genetic algorithms; Hardware; Humans; Stochastic processes; Circuit Optimization; Evolutionary Algorithm; Evolvable Hardware; Genetic Algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location
Busan
Print_ISBN
978-1-4244-2598-3
Electronic_ISBN
978-1-4244-2599-0
Type
conf
DOI
10.1109/SOCDC.2008.4815652
Filename
4815652
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