Title :
A new processor architecture for digital signal transport systems
Author :
Inamori, Minoru ; Ishii, Kenji ; Tsutsui, Akihiro ; Shirakawa, Kazuhiro ; Nakada, Hiroshi ; Miyazaki, Toshiaki
Author_Institution :
NTT Opt. Network Syst. Labs., Yokosuka, Japan
Abstract :
This paper proposes a new processor architecture for manipulating protocols in digital signal transport systems. To realize flexible and high-performance digital signal transport systems, the architecture has unique application-specific hardware with a core CPU. It is derived from an analysis of functions in real systems. A computer simulation confirms the efficiency of the architecture
Keywords :
application specific integrated circuits; asynchronous transfer mode; computer architecture; performance evaluation; protocols; signal processing; telecommunication computing; virtual machines; ATM communication; CPU; application-specific hardware; computer simulation; digital signal transport systems; flexible system; high-performance system; processor architecture; protocols; Central Processing Unit; Control systems; Degradation; Field programmable gate arrays; Frequency estimation; Hardware design languages; Pipeline processing; Signal processing; Software performance; Transport protocols;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8206-X
DOI :
10.1109/ICCD.1997.628863
