A new processor architecture for digital signal transport systems

Author

Inamori, Minoru ; Ishii, Kenji ; Tsutsui, Akihiro ; Shirakawa, Kazuhiro ; Nakada, Hiroshi ; Miyazaki, Toshiaki

Author_Institution

NTT Opt. Network Syst. Labs., Yokosuka, Japan

fYear

1997

fDate

12-15 Oct 1997

Firstpage

157

Lastpage

162

Abstract

This paper proposes a new processor architecture for manipulating protocols in digital signal transport systems. To realize flexible and high-performance digital signal transport systems, the architecture has unique application-specific hardware with a core CPU. It is derived from an analysis of functions in real systems. A computer simulation confirms the efficiency of the architecture

Keywords

application specific integrated circuits; asynchronous transfer mode; computer architecture; performance evaluation; protocols; signal processing; telecommunication computing; virtual machines; ATM communication; CPU; application-specific hardware; computer simulation; digital signal transport systems; flexible system; high-performance system; processor architecture; protocols; Central Processing Unit; Control systems; Degradation; Field programmable gate arrays; Frequency estimation; Hardware design languages; Pipeline processing; Signal processing; Software performance; Transport protocols;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-8206-X

Type

conf

DOI

10.1109/ICCD.1997.628863

Filename

628863