An efficient array architecture with data-rings for 3-step hierarchical search block matching algorithm

Author

Lai, Yewng-Kang ; Chen, Liang-Gee ; Shen, Jun-Fu

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

2

fYear

1997

fDate

9-12 Jun 1997

Firstpage

1361

Abstract

This paper describes an efficient 9-cells array architecture with data-rings for the 3-step hierarchical search block-matching algorithm. With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator-tree structure can be used to simplify the control scheme and reduce latency, respectively. In addition, we utilize a three-half-search-area scheme to reduce external memory access and interconnection. The results demonstrate that the array architecture with the data-rings gives short latency and low input ports. It also provides a high normalized throughput solution for the 3SHS

Keywords

CMOS digital integrated circuits; VLSI; data compression; digital signal processing chips; image matching; motion compensation; parallel algorithms; parallel architectures; video coding; 3-step block matching algorithm; CMOS DSP chip; array architecture; comparator-tree structure; data-rings; external memory access reduction; hierarchical search block matching algorithm; latency reduction; low input ports; raster-scanned data flow structure; three-half-search-area scheme; Bandwidth; Computational complexity; Computer architecture; Delay; Kernel; Motion estimation; Real time systems; Throughput; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.622121

Filename

622121