DocumentCode :
3158657
Title :
All-digital phase-locked loop with an adaptive bandwidth design procedure
Author :
Chau, Yawgeng A. ; Chen, Chen-Feng
Author_Institution :
Yuan Ze Univ., Chungli, Taiwan
fYear :
2009
fDate :
7-9 Jan. 2009
Firstpage :
89
Lastpage :
92
Abstract :
A design method of a second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is developed. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived. With an ADB-ADPLL, the loop bandwidth and lock-in time are balanced. According to the design criterion, the ratio of the loop noise bandwidth to the reference input frequency will be a constant if the sampling frequency is maintained as a fixed multiplier of the input reference frequency. A design example of the ADB-ADPLL is illustrated, where simulation results are presented for a performance demonstration.
Keywords :
Z transforms; digital phase locked loops; integrated circuit design; ADB-ADPLL; all-digital phase-locked loop; continuous-time PLL; fixed multiplier; lock-in time; loop noise bandwidth; reference input frequency; sampling frequency; second-order adaptive-bandwidth phase-locked loop; z-transform; Adaptive signal processing; Bandwidth; Circuit noise; Design methodology; Digital filters; Digital integrated circuits; Phase frequency detector; Phase locked loops; Signal design; Transfer functions;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Intelligent Signal Processing and Communication Systems, 2009. ISPACS 2009. International Symposium on
Conference_Location :
Kanazawa
Print_ISBN :
978-1-4244-5015-2
Electronic_ISBN :
978-1-4244-5016-9
Type :
conf
DOI :
10.1109/ISPACS.2009.5383893
Filename :
5383893
Link To Document :
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