A programmable DCO-based fast-locking clock generator

A programmable DCO-based fast-locking clock generator is presented. With a resettable DCO, the clock generator achieves similar jitter performance as conventional MDLL and avoids the initial delay constraints by resetting the output clock every two reference cycles. Compared with the previous work, a shorter locking time is obtained. The proposed clock generator is simulated with generic 1.8 V-0.18 ¿m CMOS process. The clock multiplication ratio can be programmed from 2 to 15. The frequency range of the input and output clock are 16.7 ~ 212.5 MHz and 250 ~ 425 MHz, respectively, dissipating less than 32 mW at all operating frequencies.