Title :
Monolithic mixed-mode implementation of sum-of-product arrays for performing binary morphological image processing
Author :
Spencer, Ronald G. ; Sanchez-Sinencio, Edgar
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
This paper presents a monolithic mixed-mode implementation of sum-of-product arrays that are capable of performing morphological image processing in silicon. The digital equations of the two basic morphological operations, erosion and dilation, are rewritten in a local, mixed-mode form to facilitate hardware implementation and results are shown for a 3×3 selective element array fabricated in silicon
Keywords :
elemental semiconductors; image coding; image processing equipment; mathematical morphology; mixed analogue-digital integrated circuits; silicon; binary morphological image processing; digital equations; dilation; erosion; hardware implementation; mixed-mode implementation; selective element array; sum-of-product arrays; Aggregates; Equations; Hardware; Image analysis; Image processing; Morphological operations; Morphology; Pixel; Silicon; Video coding;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.622172
