DocumentCode
3158703
Title
A high-parallelism reconfigurable permutation network for IEEE 802.11n??802.16e LDPC decoder
Author
Chen, Zhixiang ; Zhao, Xiongxin ; Peng, Xiao ; Zhou, Dajiang ; Goto, Satoshi
Author_Institution
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Tokyo, Japan
fYear
2009
fDate
7-9 Jan. 2009
Firstpage
85
Lastpage
88
Abstract
In this paper, we proposed a high-parallelism permutation network (PN) based on Benes network (BN) for LDPC decoder applied for IEEE 802.11n and 802.16e standards. By exploiting the symmetric property of BN, several groups of data can be cyclically shifted concurrently by our proposed network. Compared to the previous works our proposed PN achieves up to 4 times parallelism while maintaining small implementation area and high frequency. Additionally, based on the proposed PN, we present the architecture of a high-parallelism decoder of which the throughput does not decrease when decoding a short code.
Keywords
IEEE standards; decoding; parity check codes; wireless LAN; Benes network; IEEE 802.11n LDPC decoder; IEEE 802.16e LDPC decoder; high-parallelism reconfigurable permutation network; Bit error rate; Code standards; Decoding; Electronic mail; Error correction codes; Hardware; Intelligent networks; Parity check codes; Phase change materials; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Signal Processing and Communication Systems, 2009. ISPACS 2009. International Symposium on
Conference_Location
Kanazawa
Print_ISBN
978-1-4244-5015-2
Electronic_ISBN
978-1-4244-5016-9
Type
conf
DOI
10.1109/ISPACS.2009.5383896
Filename
5383896
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