• DocumentCode
    3159018
  • Title

    TIPO: A heuristic algorithm for delay constrained power optimization

  • Author

    Zhou, Shuzhe ; Yao, Hailong ; Zhou, Qiang

  • Author_Institution
    Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
  • fYear
    2011
  • fDate
    16-18 April 2011
  • Firstpage
    5457
  • Lastpage
    5460
  • Abstract
    In this paper, we present TIPO, a heuristic algorithm for timing constrained power optimization. The algorithm utilizes Dynamic Programming-like (DP_like) search method with consistency iteration and a fast gradient-based multiplier selection method that provides an effective set of Lagrange multipliers. Compared to the previous subgradient method provided by DP_like approach, TIPO is considerably faster and does not have the inefficiencies due to difficulties to determine initial vector of multipliers and the step size for updating multipliers. We compared the two algorithms on ISCAS85 benchmarks. On average TIPO is 54 times faster than the previously published algorithm and can reach tight delay constraint which cannot be reached by DP_like approach.
  • Keywords
    dynamic programming; electron multipliers; iterative methods; DP_like search method; ISCAS85 benchmarks; Lagrange multipliers; dynamic programming-like; heuristic algorithm; iteration; multiplier selection method; subgradient method; tight delay constraint; timing constrained power optimization; Algorithm design and analysis; Convergence; Delay; Heuristic algorithms; Logic gates; Optimization; Vt assignment; gate sizing; power optimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Consumer Electronics, Communications and Networks (CECNet), 2011 International Conference on
  • Conference_Location
    XianNing
  • Print_ISBN
    978-1-61284-458-9
  • Type

    conf

  • DOI
    10.1109/CECNET.2011.5768785
  • Filename
    5768785