Title :
A design verification kit for passive RFID system on a Chip
Author :
Park, Chan-Won ; Kim, Bo-Gwan
Author_Institution :
Electron. & Telecommun. Res. Inst., Daejeon
Abstract :
The spread of RFID application need IC-based solution to reduce the size and cost of reader. The IC result and architecture of design verification kit for UHF band passive RFID system on a chip is presented in this paper. The kit includes process core, RFID digital baseband, 10 bit-differention DAC/ADC, RF based on direct-conversion architecture, user interface block and software. RFID protocol meets the EPC Class-1 Generation 2 and ISO-18000-6C standards. The Chip made by verifying reader protocol using this kit have similar architecture and can cover all passive RFID frequency range from 860 MHz to 960MHz and provide low power consumption as 78 mA from 1.8 V when output power is +5 dBm. The package is 8 mm times 8 mm CABGA from 5 mm times 5 mm die area.
Keywords :
ISO standards; analogue-digital conversion; digital-analogue conversion; integrated circuit design; radiofrequency identification; radiofrequency integrated circuits; system-on-chip; ADC; DAC; EPC Class-1 Generation 2 standard; ISO-18000-6C standard; RFID digital baseband; current 78 mA; design verification kit; direct-conversion architecture; frequency 860 MHz to 960 MHz; passive RFID frequency; reader protocol; system-on-a-chip; user interface block; voltage 1.8 V; Baseband; Computer architecture; Costs; Energy consumption; Passive RFID tags; Protocols; Radio frequency; Radiofrequency identification; UHF integrated circuits; User interfaces; ISO18000-6C; RFID; UHF; chip; verification;
Conference_Titel :
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-2598-3
Electronic_ISBN :
978-1-4244-2599-0
DOI :
10.1109/SOCDC.2008.4815713
