Title :
A 10ps Jitter 2 Clock Cycle Lock Time Cmos Digital Clock Generator Based On An Interleaved Synchronous Mirror Delay Scheme
Author :
Saeki, T. ; Nakamura, H. ; Shimizu, J.
Author_Institution :
NEC Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211, Japan
Conference_Titel :
VLSI Circuits, 1997. Digest of Technical Papers., 1997 Symposium on
Print_ISBN :
4-930813-76-X
DOI :
10.1109/VLSIC.1997.623831
