Title :
Design of On-Chip Debug System for embedded processor
Author :
Park, Hyungbae ; Xu, Jingzhe ; Park, Jusung ; Ji, Jung-Hoon ; Woo, Gyun
Author_Institution :
Dept. of Electron. Eng., Pusan Nat. Univ., Busan
Abstract :
In this paper, we introduce on-chip debug system (OCDS) which supports symbolic debugging at c-level using OCD integrated Debug-logic into target processor. The OCDS consist of SW debugger that supports a functionality of symbolic debugging, OCD (on-chip debugger) serving as a debugger of internal state of target processor, and Interface & Control block interfacing SW debugger and OCD. After OCD block is interfaced with 32 bit RISC processor core and then implemented with FPGA, OCD is connected by Interface & Control block, and SW debugger. The verification of the design is carried out through device recognition, carrying-out instructions of JTAG(joint test action group), reading and writing the internal registers of the processor and memory, and checking the emulation functions such as setting break-points and watch points.
Keywords :
computer debugging; embedded systems; field programmable gate arrays; integrated circuit design; microcomputers; microprocessor chips; program debugging; reduced instruction set computing; system-on-chip; 32bit RISC processor; FPGA; break-points; c-level; embedded processor; emulation functions; integrated debug-logic; interface & control block; internal registers; internal state; on-chip debug system; symbolic debugging; watch points; Debugging; Emulation; Field programmable gate arrays; Read-write memory; Reduced instruction set computing; Registers; System-on-a-chip; Testing; Watches; Writing; GDB; JTAG; On-Chip Debugger; component;
Conference_Titel :
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-2598-3
Electronic_ISBN :
978-1-4244-2599-0
DOI :
10.1109/SOCDC.2008.4815725
