Title :
Memory Efficient Block-Serial Architecture for Programmable, Multi-Rate Multi-Length LDPC Decoder
Author :
Zhou, Xiyu ; Zhang, Zhaoyang
Author_Institution :
Zhejiang Univ., Hangzhou
Abstract :
This paper presents a flexible decoder architecture which supports twelve combinations of code lengths-576, 1152, 1728, 2304 bits and code rates-1/2, 2/3, 3/4 for block-serial irregular LDPC codes based on the IEEE 802.16e standard [1]. Approximate-Min Scheme is used to increase memory efficiency during message processing. At least 68.4% extrinsic message memory is saved and this reduction increases with the code rate. A prototype of the LDPC decoder has been implemented and tested on an Ateral FPGA.
Keywords :
WiMax; field programmable gate arrays; mobile radio; parity check codes; Ateral FPGA; IEEE 802.16e standard; approximate-min scheme; flexible decoder architecture; memory efficient block-serial architecture; message processing; multirate multilength LDPC decoder; Belief propagation; Bit error rate; Code standards; Decoding; Field programmable gate arrays; Hardware; Memory architecture; Parity check codes; Phase change materials; Prototypes; A-Min; Block-Serial; IEEE802.16e; LDPC; Memory Efficient; Multi-Length; Multi-Rate; Programmable;
Conference_Titel :
Communications and Networking in China, 2007. CHINACOM '07. Second International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-1009-5
Electronic_ISBN :
978-1-4244-1009-5
DOI :
10.1109/CHINACOM.2007.4469593
