Title :
High performance IPC hardware accelerator and communication network for MPSoCs
Author :
Koo, Moonmo ; Chae, Soo-Ik
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul
Abstract :
In this paper, we explain a configurable IPC module for multimedia MPSoCs, which was implemented in a MPW chip that include three ARM7 CPU cores. According to the test results for an M-JPEG and a H.264 decoder, its IPC synchronization overheads are not more than 1% when the synchronization period is about 5000 cycles.
Keywords :
multimedia systems; multiprocessing systems; synchronisation; system-on-chip; ARM7 CPU cores; H.264 decoder; IPC synchronization overheads; M-JPEG; MPW chip; communication network; high performance IPC hardware accelerator; multimedia MPSoC; Communication networks; Computer networks; Costs; Decoding; Frequency synchronization; Hardware; Performance gain; Processor scheduling; Testing; Yarn; H.264; IPC; MPSoC; multimedia; synchronization;
Conference_Titel :
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-2598-3
Electronic_ISBN :
978-1-4244-2599-0
DOI :
10.1109/SOCDC.2008.4815730
