Fast prototyping of an ASIC for ATM application using a synthesizable VHDL flexible library

Describes our design experience on fast prototyping with the development of an ASIC for ATM applications from the specification to the final implementation. The main goal of fast and safe prototyping is reached by using the CSELT Intellectual Properties Library of parametric macro-modules. This is a synthesizable library composed of a set of modules, written in RT-level VHDL and implementing functions commonly used in telecom applications. The developed circuit performs the following main functions: UTOPIA/PB interface conversion for both the physical and ATM sides, and ATM cell header processing. The circuit is intended to be used in an ATM switching system and has been designed using a 0.5 μm CMOS sea-of-gates library (3.3 V). It has a complexity of 70 kgates and an operational frequency of 33 MHz. The maximum throughput is 155 Mbit/s. It has been developed in approximately three months