Title :
Clustering and load balancing for buffered clock tree synthesis
Author :
Mehta, Ashish D. ; Chen, Yao-Ping ; Menezes, Noel ; Wong, D.F. ; Pilegg, L.T.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
Buffers in clock trees introduce two additional sources of skew: the first source of skew is the effect of process variations on buffer delays. The second source of skew is the imbalance in buffer loading. We propose a buffered clock tree synthesis methodology whereby we first apply a clustering algorithm to obtain clusters of approximately equal capacitance loading. We drive each of these clusters with identical buffers. A sensitivity based approach is then used for equalizing the Elmore delay from the buffer output to all of the clock nodes. The skew due to load imbalance is minimized concurrently by matching a higher-order model of the load by wire sizing and wire lengthening. We demonstrate how this algorithm can be used recursively to generate low-skew buffered clock trees
Keywords :
VLSI; circuit optimisation; clocks; delays; integrated circuit design; minimisation; resource allocation; trees (mathematics); Elmore delay; buffer delays; buffer loading; buffer output; buffered clock tree synthesis; capacitance loading; clustering; load balancing; low-skew buffered clock trees; process variation; sensitivity based approach; skew; skew minimization; wire lengthening; wire sizing; Capacitance; Clocks; Clustering algorithms; Contracts; Delay effects; Frequency; Load management; Load modeling; Tree data structures; Wire;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8206-X
DOI :
10.1109/ICCD.1997.628871