Title :
Impact of nanometer transistor on analog performance
Author :
Khari bin A´ain, A. ; Zakaria, Mohamad Asfa Husaini Bin ; Khor, J.G. ; Hui, See Jin
Author_Institution :
Univ. of Technol. Malaysia, Skudai, Malaysia
Abstract :
There is a serious concern on the time to market the product as transistor size continues to shrink. This is especially true in analog IC design where the impact on new process would require deep understanding of its parameters on design specifications. The nature of analog specifications which oppose each other adds more complexity in the fine tune design process. This paper explores this issue, concentrating on the impact of transistor size scaling on analog design in CMOS technology. Circuit performance-voltage gain, power dissipation, output voltage swing and cut-off frequency are observed throughout this paper to analyze the impact of transistor size scaling. Predictive transistor model (PTM) is used in this project for technology process of 130 nm, 90 nm, 65 nm, 45 nm and 32 nm.
Keywords :
CMOS analogue integrated circuits; analogue circuits; integrated circuit design; transistors; CMOS technology; analog IC design; analog specification; cut-off frequency; nanometer transistor; output voltage swing; power dissipation; predictive transistor model; size 130 nm; size 32 nm; size 45 nm; size 65 nm; size 90 nm; transistor size scaling; voltage gain; Analog integrated circuits; CMOS technology; Cutoff frequency; Performance analysis; Performance gain; Power dissipation; Process design; Time to market; Transistors; Voltage;
Conference_Titel :
Innovative Technologies in Intelligent Systems and Industrial Applications, 2009. CITISIA 2009
Conference_Location :
Monash
Print_ISBN :
978-1-4244-2886-1
Electronic_ISBN :
978-1-4244-2887-8
DOI :
10.1109/CITISIA.2009.5224206