CMOS gate delay models for general RLC loading

Gate and cell level timing analysis remains popular yet inherently incompatible with RC and RCL interconnect loads. The Ceff concept was proposed in Qian et. al. (1994) to model the interaction of empirical gate/cell delay models and RC loads. The most efficient Ceff model works in terms of precharacterizing the parameters of a time varying Thevenin voltage source model (in series with a fixed resistor) over a wide range of effective capacitance load values. In this paper we generalize this Thevenin equivalent Ceff model to enable future technologies which may include reduced supply voltages and RCL loads, without further complicating the Ceff algorithm or iterations