DocumentCode :
3160342
Title :
Bit-Streams: Applications in Neural Network Implementation
Author :
Patel, N.D. ; Nguang, S.K. ; Coghill, G.G.
Author_Institution :
Univ. of Auckland, Auckland
fYear :
2007
fDate :
9-13 July 2007
Firstpage :
4780
Lastpage :
4785
Abstract :
A new method for the parallel hardware implementation of artificial neural network (ANN) using digital techniques is presented. Uniformly weighted bit-streams are used to represent bipolar analogue signals. Operations necessary for neural network behaviour like summing, scaling and squashing have been implemented and presented. The bit- stream architecture is inherently parallel in nature and easily implemented on an field programmable gate array (FPGA) using standard hardware description language (HDL). This technique has been demonstrated using two standard pattern classifiers and a non-linear function approximator.
Keywords :
field programmable gate arrays; function approximation; hardware description languages; neural chips; artificial neural network; bipolar analogue signals; field programmable gate array; hardware description language; nonlinear function approximator; parallel hardware; uniformly weighted bit-streams; Application specific integrated circuits; Artificial neural networks; Field programmable analog arrays; Field programmable gate arrays; Hardware design languages; Logic; Neural network hardware; Neural networks; Pulse modulation; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
American Control Conference, 2007. ACC '07
Conference_Location :
New York, NY
ISSN :
0743-1619
Print_ISBN :
1-4244-0988-8
Electronic_ISBN :
0743-1619
Type :
conf
DOI :
10.1109/ACC.2007.4282258
Filename :
4282258
Link To Document :
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