• DocumentCode
    316043
  • Title

    Silicon MOSFET scaling beyond 0.1 micron

  • Author

    Iwai, Hiroshi

  • Author_Institution
    Lab. of Microelectron. Eng., Toshiba Corp., Kawasaki, Japan
  • Volume
    1
  • fYear
    1997
  • fDate
    14-17 Sep 1997
  • Firstpage
    11
  • Abstract
    This paper gives an overview of CMOS scaling in the range of sub-0.1 μm. Recent advance in the downsizing of MOSFETs by using various new techniques is described. Possible limitation and of MOSFET downswing is predicted. A future concept of silicon LSIs in 2010´s is discussed
  • Keywords
    CMOS integrated circuits; MOSFET; elemental semiconductors; integrated circuit design; integrated circuit technology; large scale integration; reviews; silicon; technological forecasting; 0.1 micron; CMOS scaling; Si; Si MOSFET scaling; silicon LSIs; Digital circuits; Large scale integration; Lithography; MOSFET circuits; Power MOSFET; Propagation delay; Silicon; Space charge; Switches; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics, 1997. Proceedings., 1997 21st International Conference on
  • Conference_Location
    Nis
  • Print_ISBN
    0-7803-3664-X
  • Type

    conf

  • DOI
    10.1109/ICMEL.1997.625168
  • Filename
    625168
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=316043