VLSI design and implementation of the entropy decoder for multi-format video decoding algorithms

Author

Xu, Chaoran ; Liu, Leibo ; Yin, Shouyi ; Lei, Hao ; Zhao, Jing ; Chen, Zheng ; Yang, Jun ; Wei, Shaojun

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2011

fDate

16-18 April 2011

Firstpage

938

Lastpage

942

Abstract

The entropy decoder proposed in this paper was implemented in VLSI (65nm process). It supports video decoding algorithms for three most popular video standards, H.264, AVS and MPEG-2. The decoding modules of H.264, AVS and MPEG-2 have some shared components, which greatly reduces the cost of hardware resources. Verification results showed that when exploiting a 200MHz working frequency, the entropy decoder can achieve 1080p@30fps for H.264, AVS and MPEG-2. This paper mainly focuses on the following aspects: the entropy decoder architecture and H.264, AVS and MPEG-2 decoding modules implementation.

Keywords

VLSI; decoding; video coding; AVS; H.264; MPEG-2; VLSI design; entropy decoder architecture; frequency 200 MHz; multiformat video decoding algorithms; size 65 nm; Decoding; Electromagnetic interference; Entropy; Streaming media; Transform coding; Very large scale integration; Video coding; AVS; Entropy Decoder; H.264; MPEG-2; Multi-media; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, Communications and Networks (CECNet), 2011 International Conference on

Conference_Location

XianNing

Print_ISBN

978-1-61284-458-9

Type

conf

DOI

10.1109/CECNET.2011.5768872

Filename

5768872