Fine Pitch Au-SnAgCu Joint-in-via Flip-Chip Packaging

One of the obstacles for wide adoption of flip chip in semiconductor packaging lies in the geometry pitch mismatch between die and substrate. This is due to the lagging advancement in substrate designs meant to satisfy the corresponding pad pitch on the die. This paper introduces an innovative joint-in-via (JIV) architecture to improve pad pitch resolutions on substrates. Different micro-via formation techniques (mechanical punch, chemical etch and laser) are assessed on both rigid and flexible substrate to realize the JIV architecture. A 70 mum-pitch substrates with a landing pad size of 50 mum has been successfully implemented for direct flip- chip application. At a larger pad pitch, the JIV offers a large receiving pad size and enables the use of conventional die bonders for flip-chip bonding. A solid-liquid interdiffusion bonding technique, using compressive force (SLICF), was chosen with the Au-SnAgCu solder system to achieve an instantaneous fluxless, lead-free, flip-chip bonding. Intermetallic analyses were identified using Scanning Electron Microscope and Energy-dispersive X-ray analysis to study the Au-SnAgCu system. Preliminary package assessment showed that the JIV using Au-SnAgCu is able to pass the standard reliability tests.