A hardware implementation of a binary neural image processor

Author

Kennedy, J.V. ; Austin, J. ; Cass, B.

Author_Institution

York Univ., UK

fYear

1995

fDate

4-6 Jul 1995

Firstpage

465

Lastpage

469

Abstract

The paper presents the work that has resulted in the sum and threshhold (SAT) processor; a dedicated hardware implementation of a binary neural image processor. The SAT processor is aimed specifically at supporting the ADAM algorithm and is currently being integrated into a new version of the C-NNAP parallel image processor. The SAT processor performs binary matrix multiplications, a task that is computationally complex for a CPU with a standard instruction set. It can perform the matrix multiplication and thresholding between 100 and 200 times faster than the DSP32C that uses an in-house produced dedicated coprocessor. This speed-up will allow the SAT to process images of up to 220×220 pixels at 25-Hz frame rates

Keywords

application specific integrated circuits; digital signal processing chips; image processing equipment; matrix multiplication; neural net architecture; parallel architectures; 25 Hz; 25-Hz frame rates; ADAM algorithm; C-NNAP parallel image processor; binary matrix multiplications; binary neural image processor; hardware implementation; sum and threshhold processor; thresholding;

fLanguage

English

Publisher

iet

Conference_Titel

Image Processing and its Applications, 1995., Fifth International Conference on

Conference_Location

Edinburgh

Print_ISBN

0-85296-642-3

Type

conf

DOI

10.1049/cp:19950702

Filename

465515