Title :
Leakage behavior of underlap FinFET structure: A simulation study
Author :
Saini, Gaurav ; Rana, Ashwani K. ; Pal, Pankaj Kr ; Jadav, Sunil
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol. Hamirpur, Hamirpur, India
Abstract :
Bulk MOSFET is reaching to its physical limit with the advancement of technology. The key factor which influences the performance of bulk MOSFET in nano regime is the gate oxide thickness. In this work an attempt has been made to analyze the underlap FinFET structure using 2D simulation. ITRS 2009 high performance (HP) updates for the year of 2015 is used in this work. Study of n-type underlap FinFET structure is carried out to analyze the effects of metal gate with high-k dielectric. Use of high-k dielectrics with metal gate at a given EOT can improve the gate leakage current without harming the device performance. Underlap structure provides an improvement in the off-state leakage current than the overlap structure. Effects of gate workfuction variation on the performance of underlap FinFET structure is also studied in this paper.
Keywords :
MOSFET; high-k dielectric thin films; leakage currents; 2D simulation; EOT; ITRS 2009; MOSFET; gate oxide thickness; high-k dielectric; metal gate leakage current; n-type underlap FinFET structure; off-state leakage current; Dielectric constant; FinFETs; Leakage current; Logic gates; MOSFET circuits; Performance evaluation; Threshold voltage; Double Gate; High performance (HP); Low operating power (LOP); Underlap FinFET;
Conference_Titel :
Computer and Communication Technology (ICCCT), 2010 International Conference on
Conference_Location :
Allahabad, Uttar Pradesh
Print_ISBN :
978-1-4244-9033-2
DOI :
10.1109/ICCCT.2010.5640528
