Analytical modeling of the device conductances of lightly doped drain (LDD) MOSFETs

A new and simplistic approach is proposed to model the device conductances of submicrometer Lightly Doped Drain (LDD) MOSFETs. We model the LDD MOSFET as a conventional MOSFET with, a series resistance. The series resistance in the channel region is accounted as a voltage drop at the drain end by replacing the drain to source voltage with an effective drain to source voltage V_deff. This method is much simpler and less time consuming in comparison with many other modeling approaches in which the lengthy procedure of calculating the series resistance and electric field is involved. New closed form expressions for the transconductance and the drain conductance are derived. The channel resistance is also evaluated from the drain conductance. A comparative study of the transconductance, drain conductance and channel resistance of LDD and conventional MOSFETs is carried out. The results show a lower current driving capability of the drain engineered MOS devices over the conventional ones