Avalanche characteristics of MOS transistors

Author

Rossel, P. ; Tranduc, H. ; Montcoqut, D. ; Charitat, G. ; Pagès, I.

Author_Institution

Lab. d´´Autom. et d´´Anal. des Syst., CNRS, Toulouse, France

Volume

1

fYear

1997

fDate

14-17 Sep 1997

Firstpage

371

Abstract

This paper reviews the mechanisms that induce a negative resistance in MOS transistors operating in the avalanche mode. For n-channel devices, it is shown that snapback can be associated with the “body effect” of the MOS transistor. At high current levels, carrier injection by the source, turn-on of the parasitic n-p-n transistor, and excess carrier charge in the pinched channel are taken into account. Subthreshold currents may also be involved. The associated safe operating area limits are determined analytically. Induced failures in multi-cell power MOSTs are also discussed. An electrical model for the simulation of the device characteristics in the avalanche regime is suggested

Keywords

avalanche breakdown; negative resistance; power MOSFET; semiconductor device models; semiconductor device reliability; MOS transistors; avalanche characteristics; body effect; carrier injection; electrical model; excess carrier charge; high current levels; induced failures; multi-cell power MOSTs; n-channel devices; negative resistance; parasitic n-p-n transistor turn-on; pinched channel; safe operating area limits; simulation; snapback; subthreshold currents; Avalanche breakdown; Bipolar transistors; Breakdown voltage; Electric breakdown; Electric resistance; Electrodes; Immune system; Logic circuits; Logic devices; MOSFETs;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 1997. Proceedings., 1997 21st International Conference on

Conference_Location

Nis

Print_ISBN

0-7803-3664-X

Type

conf

DOI

10.1109/ICMEL.1997.625274

Filename

625274