DocumentCode :
3161115
Title :
Design Reliable Large FCTEBGA through Integrated Experimental and Numerical Method
Author :
Luan, Jing-En
Author_Institution :
STMicroelectronics, Singapore
fYear :
2007
fDate :
10-12 Dec. 2007
Firstpage :
774
Lastpage :
778
Abstract :
Flip chip thermal enhanced ball grid array (FCTEBGA) package has been introduced in recent years to meet the rising demand for higher pin count IC, higher performance and better thermal management devices for high-end computers and networks applications. However, there are many factors which affect solder joint reliability such as material, package architecture, heat spreader design, substrate, PWB, etc. Most importantly, the effect of substrate layer & trace, PWB layer, package / board warpage on solder joint reliability is not well understood due to complexity. The errors induced by material characterization, assembly process, etc were no considered during numerical analysis. In this paper, both experiments and modeling were performed on 5 test vehicles with package size from 17times17 mm to 55times55. Thermoire was also used to characterize FCTEBGA mechanical behavior in each assembly process. Three-dimensional finite element model has been created for parametric study on warpage and solder joint fatigue performance. Three level correlations were proposed. Good correlation was achieved between measured warpage and modeling results. Based on the good correlation in package / board warpage, good life prediction model was obtained based on correlation of strain energy density with thermal cycling fatigue testing lives of FCBGA packages.
Keywords :
assembling; ball grid arrays; finite element analysis; flip-chip devices; reliability; 3D finite element model; FCTEBGA; assembly process; flip chip thermal enhanced ball grid array package; mechanical behavior; numerical method; package size; solder joint fatigue performance; strain energy density; thermal cycling fatigue testing; thermoire; warpage; Application specific integrated circuits; Assembly; Computer network management; Computer network reliability; Electronics packaging; Fatigue; Flip chip; Integrated circuit packaging; Soldering; Thermal management;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2007. EPTC 2007. 9th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-1323-2
Electronic_ISBN :
978-1-4244-1323-2
Type :
conf
DOI :
10.1109/EPTC.2007.4469745
Filename :
4469745
Link To Document :
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