• DocumentCode
    3161175
  • Title

    Determination of Critical Parameters for Crosstalk Faults between On-chip Interconnects using Worst-Case Methods

  • Author

    Vudathu, Shyam Praveen ; Duganapalli, Kishore K. ; Palit, Ajoy K. ; Laur, Rainer ; Anheier, Walter

  • Author_Institution
    Univ. of Bremen, Bremen
  • fYear
    2007
  • fDate
    10-12 Dec. 2007
  • Firstpage
    267
  • Lastpage
    271
  • Abstract
    Interconnects being the limiting factor for both performance and density in today´s VLSI systems, interconnect parasitics are considered to be the prime sources of signal integrity problems. Line inductance and/or mutual inductance in certain interconnect lines usually give rise to overshoots and undershoots in voltage waveforms which may cause reliability concerns in circuits, cause glitches and may lead to false transitions at the gate output. Therefore, it is important to track down the limiting values or the critical parameters of influential parameters below which a fault tolerant behavior of the device can be guaranteed. Earlier, there have been some analytical approaches for calculating these critical values, which are always prone to the availability of direct analytical equations for each and every case. In this paper, we explored a numerical based technique called the advanced worst-case method to track down the critical parameter set. The worst-case method taken up in this work is capable of accurately and efficiently calculating the critical values in diverse scenarios. The concept has been validated on a comprehensive distributed crosstalk fault model that considers RLGC parameters, coupling parameters together with the strengths of the driver and the receiver.
  • Keywords
    VLSI; circuit reliability; crosstalk; integrated circuit interconnections; RLGC parameters; VLSI systems; advanced worst-case method; circuit reliability; coupling parameters; critical parameter determination; crosstalk faults; direct analytical equations; distributed crosstalk fault model; fault tolerant behavior; interconnect lines; interconnect parasitics; line inductance; mutual inductance; on-chip interconnects; signal integrity problems; voltage waveforms; worst-case methods; Circuit faults; Crosstalk; Delay; Driver circuits; Inductance; Integrated circuit interconnections; Mutual coupling; Parasitic capacitance; Semiconductor device modeling; Transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference, 2007. EPTC 2007. 9th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-1323-2
  • Electronic_ISBN
    978-1-4244-1323-2
  • Type

    conf

  • DOI
    10.1109/EPTC.2007.4469748
  • Filename
    4469748