Title :
Development of low-cost and highly reliable wafer process package
Author :
Kazama, Atsushi ; Satoh, Toshiya ; Yamaguchi, Yoshihide ; Anjoh, Ichiro ; Nishimura, Asao
Author_Institution :
Mech. Eng. Res. Lab., Hitachi Ltd., Tsuchiura, Japan
Abstract :
A wafer level chip-scale-package (WLCSP) is expected to reduce the manufacturing cost of CSPs, but reliability of a solder joint for a large chip size of about 100 mm2 without underfill assembly is still in question. To meet this needs, we have developed a highly reliable and low-cost WLCSP named wafer process package phase 2 (WPP-2). The package includes a built-in stress-relaxation layer for reducing the strain of the solder bumps. To lower the manufacturing cost of the package, the stress-relaxation layer is formed by printing. The Young´s modulus and the thickness of the stress relaxation layer were optimized by finite element analysis. The package was assumed to have 10×10 mm chip and 54 Sn-Ag-Cu solder balls of 400-μm diameter placed as a grid array with the minimum pitch of 0.8 mm, and be mounted on a FR-4 motherboard. It was found that a thickness of 75-μm and a Young´s modulus of 1000 MPa are necessary for assuring no failure up to 1000 cycles under temperature cycling between -55 and 125°C. Accordingly, a resin with a Young´s modulus of about 1200 MPa at -55°C was developed for the stress relaxation layer. High reliability of the simulated WPP-2 structure was confirmed by simplified test samples made of the developed resin. Fully processed WPP-2 samples were fabricated on an 8-inch wafer. The lifetime of the solder joints mounted on the FR-4 motherboard was evaluated by the temperature cycling test. The contact resistance of none of 50 samples increased by more than 20% even after 1400 cycles, and their lifetime to 50% failure was more than 3000 cycles
Keywords :
Young´s modulus; ball grid arrays; chip scale packaging; contact resistance; failure analysis; finite element analysis; reliability; soldering; stress relaxation; -55 to 125 C; FR-4 motherboard; Sn-Ag-Cu; Young modulus; ball grid array; contact resistance; failure lifetime; finite element analysis; resin; solder joint reliability; stress relaxation layer; temperature cycling; wafer process package phase 2; wafer-level chip scale package; Assembly; Capacitive sensors; Costs; Manufacturing; Packaging; Resins; Soldering; Stress; Temperature; Wafer scale integration;
Conference_Titel :
Electronic Components and Technology Conference, 2001. Proceedings., 51st
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-7038-4
DOI :
10.1109/ECTC.2001.927681