DocumentCode :
3161411
Title :
Development of low cost, highly reliable CSP using gold-gold interconnection technology
Author :
Isozaki, Seiya ; Kimura, Takehiro ; Shimada, Toshiyasu ; Nakajima, Hirofumi
Author_Institution :
Div. of Packaging & Testing Eng., NEC Corp., Sagamihara, Japan
fYear :
2001
fDate :
2001
Firstpage :
63
Lastpage :
68
Abstract :
A low cost, highly reliable CSP (Chip Size Package) named T-G2BGA (tape gold-gold gang bond BGA), has been developed for compact, and light memory devices´ package. T-G2BGA has a structure that connects a chip and an interposer using gold-gold interconnection technology, which uses thermo-compression flip chip bonding. We studied the ways to interconnect gold stud bumps on chip and gold plated pads on tape metallurgically and succeeded in realizing a highly reliable package. T-G2BGA can realize fan-in type, real chip size, package, and fan-out type package. For the fan-out type, sidefill resin or support ring is formed on overhang tape for solder ball coplanarity. Using TEG (test element group) samples, we selected the most suitable materials and optimized flip chip bonding conditions. Consequently, 60 pin fan-in type package was fabricated under optimized conditions using selected materials and memory device, and good reliability test results were obtained. On the other hand, 60 pin fan-out type package was fabricated with optimized sidefill resin, which showed good solder ball coplanarity and solder joint reliability. The gold stud bumps and gold pads interconnection technology is considered to be low cost, highly reliable and more suitable for CSP
Keywords :
VLSI; ball grid arrays; chip scale packaging; flip-chip devices; gold; integrated circuit interconnections; Au-Au; T-G2BGA; fan-in type; fan-out type; gold plated pads; gold stud bumps; gold-gold interconnection technology; highly reliable CSP; interconnection technology; real chip size; sidefill resin; solder ball coplanarity; support ring; tape gold-gold gang bond BGA; thermo-compression flip chip bonding; Aluminum; Bonding; Chip scale packaging; Conducting materials; Costs; Flip chip; Gold; Impurities; Materials testing; Resins;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2001. Proceedings., 51st
Conference_Location :
Orlando, FL
ISSN :
0569-5503
Print_ISBN :
0-7803-7038-4
Type :
conf
DOI :
10.1109/ECTC.2001.927686
Filename :
927686
Link To Document :
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