DocumentCode :
3161528
Title :
Analysis of sampling clock jitter effect on the SNR of two RF sampling receivers
Author :
Shuangjun Bi ; Youxin Lv
Author_Institution :
Sch. of Electron. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear :
2013
fDate :
26-28 Oct. 2013
Firstpage :
394
Lastpage :
397
Abstract :
Today the RF sampling receivers have divided into direct sampling receivers with an ADC converter for low RF signals and direct pulse sampling receivers for high RF signals. Factors that affect the SNR of the two RF sampling systems are analyzed. Clock jitter is proved to be the key factor affecting RF sampling. This paper analyzes the cause of clock jitter and the relationship between jitter error and the input signal frequency, then gives the formula of SNR with jittered noise of the two receivers. Simulation results are given to verify the rational analysis. The results show that the SNR decreases with the increases of input signal frequency, and intensive jittered clock can also result in a serious deterioration of SNR.
Keywords :
analogue-digital conversion; clocks; jitter; radio receivers; signal sampling; ADC converter; RF sampling receivers; direct pulse sampling receiver; direct sampling receiver; high RF signal; low RF signal; sampling clock jitter effect; signal-to-noise ratio; Band-pass filters; Clocks; Jitter; RF signals; Radio frequency; Receivers; Signal to noise ratio; RF sampling; clock jitter; receiver; signal to noise ratio(SNR);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computational Problem-solving (ICCP), 2013 International Conference on
Conference_Location :
Jiuzhai
Type :
conf
DOI :
10.1109/ICCPS.2013.6893555
Filename :
6893555
Link To Document :
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