Title :
Reduction of signal voltage of DRAM cell induced by discharge of trapped charges in nano-meter thick dual dielectric film (SiO/sub 2//Si/sub 3/N/sub 4/)
Author :
Kumagai, J. ; Toita, K. ; Kaki, S. ; Sawada, S.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
Trap/detrap characteristics of nanometer thick SiO/sub 2//Si/sub 3/N/sub 4/ dual dielectric film and the impact of the detrapping on DRAM cell are investigated. The authors estimated net trapped charge in the film, using a new method. Trap/detrap characteristics are strongly dependent on stress bias. Deterioration of DRAM cell signal voltage due to detrapping was found. The thickness of the film and the plate bias should be optimized by considering not only leakage current through SiO/sub 2//Si/sub 3/N/sub 4/ film but also detrap of trapped charge.<>
Keywords :
DRAM chips; MOS integrated circuits; dielectric thin films; silicon compounds; DRAM cell; SiO/sub 2/-Si/sub 3/N/sub 4/; charge retention time; detrap of trapped charge; detrapping; discharge of trapped charges; dual dielectric film; film thickness optimisation; leakage current; nanometre thick dielectrics; net trapped charge; plate bias; signal voltage reduction; stress bias; Capacitance; Capacitance-voltage characteristics; Dielectric films; Electrodes; Equivalent circuits; Nanoscale devices; Random access memory; Stress; Testing; Voltage;
Conference_Titel :
Reliability Physics Symposium, 1990. 28th Annual Proceedings., International
Conference_Location :
New Orleans, LA, USA
DOI :
10.1109/RELPHY.1990.66082
