Title :
Design and packaging challenges for on-board cache subsystems using source synchronous 400 Mb/s interfaces
Author :
Pham, Nam ; Cases, Moises ; Guertin, Dave
Author_Institution :
eServer X Series, IBM Corp., Austin, TX, USA
Abstract :
This paper describes circuit and packaging design challenges encountered while attempting to optimize the source synchronous timing equations for the system level interconnects using a 200 MHz double data rate (DDR) level 3 (L3) cache subsystem. Various solutions to these challenges are presented. The delay skew budget and noise margin allocation for the various components of the optimization equations are discussed in conjunction with their associated delay skew control techniques
Keywords :
cache storage; integrated circuit design; integrated circuit interconnections; microprocessor chips; packaging; 200 MHz; delay skew; design optimization; microprocessor circuit; noise margin; on-board DDR level 3 cache subsystem; packaging; source synchronous interface; system-level interconnect; timing allocation; Clocks; Crosstalk; DRAM chips; Delay; Design optimization; Equations; Integrated circuit interconnections; Microprocessors; Packaging; Timing;
Conference_Titel :
Electronic Components and Technology Conference, 2001. Proceedings., 51st
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-7038-4
DOI :
10.1109/ECTC.2001.927706
