DocumentCode :
3161829
Title :
Multigigabit RS-CC decoder for 60-GHz systems
Author :
Penggang Jiang ; Bo Gao ; Zhenyu Xiao ; Li Su ; Depeng Jin
Author_Institution :
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
fYear :
2013
fDate :
26-28 Oct. 2013
Firstpage :
207
Lastpage :
210
Abstract :
With ultra-wide unlicensed spectrum, 60-GHz communication system has become a key candidate to achieve multigigabit throughput in short distance. This paper proposes a novel multigigabit Reed-Solomon (RS) convolutional codes (CC) decoder architecture for 60-GHz systems. In the proposed architecture, the RS and the CC codes are used as outer codes and inner codes, respectively. For RS decoder, the circuit for reformulated inversionless Berlekamp-Massey (RIBM) algorithm is proposed via double-clock methods to improve the decoding speed. For CC decoder, we adopt a balanced add-select-register-compare Viterbi decoder architecture, which breaks the decoding-speed bottleneck in traditional Viterbi decoders. The proposed RS-CC decoder has been implemented and demonstrated in a Xilinx Virtex-6 FPGA device.
Keywords :
Reed-Solomon codes; Viterbi decoding; codecs; convolutional codes; field programmable gate arrays; flip-flops; RIBM algorithm; Reed-Solomon codes; Viterbi decoder architecture; Xilinx Virtex-6 FPGA device; add-select-register-compare decoder architecture; convolutional codes; double-clock methods; frequency 60 GHz; inner codes; multigigabit RS-CC decoder architecture; outer codes; reformulated inversionless Berlekamp-Massey algorithm; ultra-wide unlicensed spectrum; Bit error rate; Clocks; Decoding; Polynomials; Throughput; Viterbi algorithm; Wireless personal area networks; Double-Clock; Multigigabit; RIBM algorithm; RS-CC decoder; Viterbi decoder;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computational Problem-solving (ICCP), 2013 International Conference on
Conference_Location :
Jiuzhai
Type :
conf
DOI :
10.1109/ICCPS.2013.6893576
Filename :
6893576
Link To Document :
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